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SC4525A
28V 3A Step-Down Switching Regulator
POWER MANAGEMENT Features

Description
The SC4525A is a constant frequency peak current-mode step-down switching regulator capable of producing 3A output current from an input ranging from 8V to 28V. The switching frequency of the SC4525A is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4525A is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4525A achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4525A is available in SOIC-8 EDP package.
Wide input range: 8V to 28V 3A Output Current 200kHz to 2MHz Programmable Frequency Precision V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant
Applications

XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs
SC4525A
Typical Application Circuit
Efficiency
V IN
10V - 28V
D1
90 80
C4 4.7mF
IN
BST
SW
Efficiency (%)
1N4148 C1 0.1mF L1
5.2mH
OUT
VIN = 12V 70 60 50 40
VIN = 24V
SS/EN
SC4525A
FB
R4 33.2k
5V/3A
COMP
ROSC
GND
C7 10nF
C8 10pF
R7 24.3k
C5 1nF
R5 18.2k
D2 20BQ030
R6 8.25k
C2 10mFX3
L1: Coiltronics CD1-5R2
C2: Murata GRM31CR60J106K C4: Murata GRM32ER71H475K
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Figure 1. 1MHz 10V -28V to 5V/3A Step-down Converter
November 8, 2007
Efficiency of the 1MHz 10V-28V to 5V/3A Step-Down Conve
SC4525A
Pin Configuration Ordering Information
Device
SC4525ASETRT()(2)
SW IN ROSC GND 1 2 3 4 9 8 7 6 5 BST FB COMP SS/EN
Package
SOIC-8 EDP Evaluation Board
SC4525AEVB
Notes: () Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant.
(8 - Pin SOIC - EDP)
Marking Information
yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E900)
2
SC4525A
Absolute Maximum Ratings
VIN Supply Voltage .................................... -0.3 to 32V BST Voltage ...................................................... 42V BST Voltage above SW .......................................... 34V SS Voltage ...................................................-0.3 to 3V FB Voltage ................................................... -0.3 to VIN SW Voltage ................................................ -0.6 to VIN SW Transient Spikes (0ns Duration)......... -2.5V to VIN +.5V Peak IR Reflow Temperature ............................... 260C ESD Protection Level(2) ....................................... 2000V
Thermal Information
Junction to Ambient () .................................... 36C/W Junction to Case () ....................................... 5.5C/W Maximum Junction Temperature........................... 50C Storage Temperature .............................. -65 to +50C Lead Temperature (Soldering) 0 sec ..................... 300C
Recommended Operating Conditions
Input Voltage Range .................................... 8V to 28V Maximum Output Current .................................... 3A
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES() Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5 standards. (2) Tested according to JEDEC standard JESD22-A4-B.
Electrical Characteristics
Unless otherwise noted, VIN = 2V, VBST = 5V, VSS = 2.2V, -40C < TA = TJ < 25C, ROSC = 2.k.
Parameter Input Supply
Input Voltage Range VIN Start Voltage VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown
Conditions
Min
8
Typ
Max
28
Units
V V mV
VIN Rising
2.70
2.82 225
2.95
VCOMP = 0 (Not Switching) VSS/EN = 0, VIN = 2V
2 40
2.6 50
mA A
Error Amplifier
Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Pin to Switch Current Gain COMP Maximum Voltage COMP Source Current COMP Sink Current VIN = 8V to 28V VFB = V, VCOMP = 0.8V 0.980 .000 0.005 -70 280 60 2 -340 .020
V %/V nA
-
dB A/V
V A
VFB = 0.9V VFB = 0.8V, VCOMP = 0.8V VFB = .2V, VCOMP = 0.8V
(Note ) ISW = -3.9A 3.9
2.35 7 25
Internal Power Switch
Switch Current Limit Switch Saturation Voltage 5. 380 6.6 600 A mV
3
SC4525A
Electrical Characteristics (Cont.)
Unless otherwise noted, VIN = 2V, VBST = 5V, VSS = 2.2V, -40C < TA = TJ < 25C, ROSC = 2.k.
Parameter
Minimum Switch On-time Minimum Switch Off-time Switch Leakage Current Minimum Bootstrap Voltage BST Pin Current
Conditions
Min
Typ
50 00
Max
50 0
Units
ns ns A V mA
ISW = -3.9A ISW = -3.9A
.8 00
2.3 50
Oscillator
Switching Frequency ROSC = 2.k ROSC = 93.k ROSC = 2.k, VFB = 0 ROSC = 93.k, VFB = 0 .04 240 0 50 .3 300 230 0 .56 360 350 70 MHz kHz kHz
Foldback Frequency
Soft Start and Overload Protection
SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current Soft-start Discharging Current Hiccup Arming SS/EN Voltage Hiccup SS/EN Overload Threshold Hiccup Retry SS/EN Voltage 0.2 0.3 .3 .7 .2 2.0 .5 2.8 0.4 .3 V V A A V V .2 V
VFB = 0 V VSS/EN = 0 V VSS/EN = .5 V VSS/EN Rising VSS/EN Falling VSS/EN Falling
.0
2.5 .9 0.6 .0
Over Temperature Protection
Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note : Switch current limit does not vary with duty cycle. 65 0 C C
4
SC4525A
Pin Descriptions
SO-8
2 3 4
Pin Name
SW IN ROSC GND
Pin Function
Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. An external resistor from this pin to ground sets the oscillator frequency. Ground pin Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board.
5
SS/EN
6 7 8 9
COMP FB BST Exposed Pad
5
SC4525A
Block Diagram
IN COMP
6
SLOPE COMP
2
+
+ EA +
S
+
+ ISEN 4.1mW OC + ILIM 20mV BST
FB
7
V1 + PWM FREQUENCY FOLDBACK
8
S R CLK
Q
POWER TRANSISTOR
ROSC
3
OSCILLATOR
R R SS/EN
5
OVERLOAD
A1
+ -
1.23V
1
SW
PWM
1
GND
4
1V
1.9V FAULT
REFERENCE & THERMAL SHUTDOWN
SOFT-START AND OVERLOAD HICCUP CONTROL
Figure 2. SC4525A Block Diagram
1.9V IC 2mA
B4 + B1
S Q R OVERLOAD
SS/EN
1V/2.15V
B2
FAULT
ID 3.5mA
_ Q
S R
OC
PWM
B3
Figure 3. Soft-start and Overload Hiccup Control Circuit
6
f
(2) 24Vin Eff
Typical Characteristics
Efficiency
VO=5V VO=3.3V VO=2.5V
(3)
SC4525A SS270 REV 6-7
SC4525A
SC4525A
90 85 80 75 70 65 60 55 50 40 0 SS270 REV 6-7 0.5
90 85 80 75 70 65 60 55 50 40
Efficiency
V O=5V V O=3.3V V O=2.5V
Feedback Voltage vs Temperature
1.02 V IN =12V 1.01 1.00 0.99 0.98 0.97
Efficiency (%)
Efficiency (%)
V O=1.5V
(5) 45
1
VIN=12V 1MHz
(6) 45
2 2.5 3 0 0.5 1 SS270 REV 6-7
VIN=24V 1MHz
1.5
1.5
2
2.5
3
VFB (V)
-50
-25
0
25
50
75
o
100 125
Load Current (A)
Load Current (A)
Temperature ( C)
1000
Frequency Setting Resistor vs Frequency
V IN =12V
Frequency vs Temperature
1.2
R OSC=93.1k
Foldback Frequency vs VFB
1.25 1
ROSC=93.1k
1.1
100
Normalized Frequency
Normalized Frequency
ROSC (k)
0.75 0.5 0.25
R OSC=12.1k
1.0
R OSC=12.1k
10
(8) OCP current
1 0 0.5 1 1.5 2 2.5
0.9
(9) BST Pin current
-50 -25 0 25 50 75 100 125 Temperature (o C)
TA =25oC
0.8
0 0.0 0.2 0.4 0.6 0.8 1.0
Frequency (MHz)
SS270 REV 6-7 SS270 REV 6-7
VFB (V)
500 450
Switch Saturation Voltage vs Switch Current
Switch Current Limit vs Temperature
5.0 4.8 100.0
BST Pin Current vs Switch Current
VIN =12V V BST-SW =5V
V CESAT (mV)
350 300 250 200 150 100 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Switch Current (A) 25oC -40 C
o
4.6 4.4 4.2 4.0 -50 -25 0 25 50
o
BST Pin Current (mA)
400
125oC
Current Limit (A)
75.0
50.0
-40oC 125oC
25.0
0.0 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4 Temperature ( C) Switch Current (A)
7
(11)
SS270 REV 6-7
Vin Shut down current
SC4525A
Typical Characteristics (Cont.)
SS270 REV 6-7
SS270 REV 6-7
VIN Thresholds vs Temperature
3.0 2.9
Start
2.5 2.0
VIN Supply Current vs Soft-Start Voltage
125oC -40oC
100 80
VIN Shutdown Current vs VIN
VSS = 0
VIN Threshold (V)
Current (mA)
Current (uA)
2.8 2.7 2.6
1.5 1.0 0.5 0.0
60 -40oC 40 20 0 125oC
t
(14) 2.5
2.4 -50 -25 0
UVLO
(15)
0 0.5 1 V SS (V) 1.5 2
SS270 REV 6-7
25
50
75
100 125
0
5
10
15 V IN (V)
20
25
30
Temperature (o C)
SS270 REV 6-7
SS270 REV 6-7
VIN Quiescent Current vs VIN
2.5 125oC 2.0 0.40
SS Shutdown Threshold vs Temperature
Soft-Start Charging Current vs Soft-Start Voltage
0.0 -0.5
SS Threshold (V)
-40 C
o
0.35
Current (uA)
Current (mA)
-1.0 -1.5 -2.0 -2.5
1.5 1.0 0.5 0.0 0 5 10 15 VIN (V) 20 25 30
125oC
0.30
-40oC
0.25
V COMP = 0 0.20 -50 -25 0 25 50
o
-3.0 75 100 125 0 0.5 1 V SS (V) 1.5 2
Temperature ( C)
8
SC4525A
Applications Information
Operation The SC4525A is a constant-frequency, peak currentmode, step-down switching regulator with an integrated 28V, 3.6A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 4.mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 20mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C and the diode D in Figure ) generates such a voltage at the BST pin for driving the power transistor. Shutdown and Soft-Start The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4525A is summarized in Table . Table 1: SS/EN operation modes
SS/EN <0.2V SS/EN to 1.23V 0.4V <0.2V 1.23V to 2.1V Mode Supply Current Shutdown 18uA @ 5Vin Mode switching Supply Current Not 2mA Shutdown 18uA @ 5Vin Switching & hiccup disabled Load dependent Not switching hiccup armed 2mA Switching & Load dependent
When the SS/EN pin is released, the soft-start capacitor is charged with an internal .6A current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, the internal bias circuit of the SC4525A turns on and the SC4525A draws 2mA from VIN. The .6A charging current turns off and the 2A current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision V reference and the other non-inverting input is tied to the output of the amplifier A. Amplifier A produces an output V = 2(VSS/EN -.23V). V is zero and COMP is forced low when VSS/EN is below .23V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above .23V. Once VSS/EN exceeds .23V, COMP is released. The regulator starts to switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V during start up. VSS/EN must be at least .83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4525A. Table 2: Fault conditions and protections Cycle-by-cycle limit at
Over current Fault Protective Action frequency programmed Cycle-by-cycle limit at limit with Cycle-by-cycle Condition Fault Protective Action
IL>ILimit, VFB>0.8V Condition
IL>ILimit, VFB>0.8V Over current current IL>ILimit, VFB<0.8V Over
programmed frequency frequency foldback Cycle-by-cycle limit with retry VSS/EN Falling Persistent over current Shutdown, then IL>ILimit, VFB<0.8V Over current SS/EN<1.9V or short circuit frequency foldback (Hiccup) VSS/EN Falling Persistent over current Shutdown, then retry Tj>160C Over temperature Shutdown SS/EN<1.9V or short circuit (Hiccup) Tj>160C Over temperature Shutdown
0.4V to 1.23V >2.1V 1.23V to 2.1V >2.1V
Switching & hiccup disabled Switching & hiccup armed
Pulling the SS/EN pin below 0.2V shuts off the regulator and reduces the input supply current to 8A (VIN = 5V).
As summarized in Table , overload shutdown is disabled during soft-start (VSS/EN<2.V). In Figure 3, the reset input of the overload latch B2 will remain high if the SS/EN voltage is below 2.V. Once the soft-start capacitor is charged above 2.V, the output of the Schmitt trigger B goes high, the reset input of B2 goes low and hiccup becomes armed.
9
SC4525A
Applications Information (Cont.)
As the load draws more current from the regulator, the current-limit comparator ILIM (Figure 2) will eventually limit the switch current on a cycle-by-cycle basis. The over-current signal OC goes high, setting the latch B3. The soft-start capacitor is discharged with (ID - IC) (Figure 3). If the inductor current falls below the current limit and the PWM comparator instead turns off the switch, then latch B3 will be reset and IC will recharge the soft-start capacitor. If over-current condition persists or OC becomes asserted more often than PWM over a period of time, then the soft-start capacitor will be discharged below .9V. At this juncture, comparator B4 sets the overload latch B2. The soft-start capacitor will be continuously discharged with (ID - IC). The COMP pin is immediately pulled to ground. The switching regulator is shut off until the soft-start capacitor is discharged below .0V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through soft-start, overload shutdown and restart until it is no longer overloaded.
AC = V R4 = R6 O - 1 down switching Vregulator in continuous-conduction 1.0 mode (CCM) is given by D= VO + VD VIN + VD - VCESAT
(2)
AC =
where VIN is the input voltage, VCESAT is the switch saturation voltage, and VD is voltage drop across the rectifying diode. DI = ( VO + VD ) (1 - D) L FSW L 1 In peak current-mode control, the PWM modulating ramp is the Vsensed current ramp of the power switch. ( + VD ) (1 - D) L1 = O This current ramp Iis absent unless the switch is turned 20% O FSW on. The intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse Iwidth. The propagation delay time required to D (1 - D) RMS _ CIN = I O immediately turn off the switch after it is turned on is the minimum controllable switch on time (TON(MIN)).
R7 = C5 = C8 =
Vo = Vc
1 Closed-loop DI ESR + DVO = measurement shows that the SC4525A L 8 SW C minimum on time is aboutF30nsOat room temperature (Figure 4). If the required switch on time is shorter than If the FB voltage falls below 0.8V because of output the minimum on time, the regulator will either skip cycles overload, then the switching frequency will be reduced. or it will jitter. SS270 REV 6-7 IO Frequency foldback helps to limit the inductor current C IN > 4 DVIN FSW when the output is hard shorted to ground. Minimum On Time vs Temperature
Fig. 4
GPWM
R7 = C5 = C8 =
During normal operation, the soft-start capacitor is charged to 2.4V.
TON(MIN) (ns)
200 190 180 170 160 150 140 130 V O =1.5V 1MHz
Setting the Output Voltage The regulator output voltage, VO, is set with an external resistive divider (Figure ) with its center tap tied to the FB pin. For a given R6 value, R4 can be found by
V R4 = R6 O - 1 1.0 V
1 V 1 A C = - 20120 log FB G R 2FC C O VO 110 CA S
100
()
VO + VD Setting the Switching Frequency D= VIN + VD - VCESAT The switching frequency of the SC4525A is set with an external resistor from the ROSC pin to ground. ( V + VD ) (1 - D) DIL On O Minimum = Time Consideration FSW L 1
The operating duty cycle of a non-synchronous step( V + VD ) (1 - D) L1 = O 20% IO FSW
-50 -25 0 1 25 50 75 100 125 1 1.0 A C = - 20 log = 15 Temperature (o C) -3 3 -6 3 .3 2 80 10 22 10 28 6.1 10
Figure 4. Variation of Minimum On Time 15.9 10 20 with Ambient Temperature R7 = = 22.3k 0.28 10 -3 To allow for transient headroom, the minimum operating 1 C5 = = 0.45nF switch 16 10 3 22.1 10 3 on time should be at least 20% to 30% higher than 2 the worst-case minimum on time. 1 C8 = = 12pF 2 600 10 3 22.1 10 3
0
L1 =
20% IO FSW
O
D
SC4525A
IRMS _ CIN = IO D (1 - D)
Vo = Vc
Applications Information (Cont.)
Minimum Off Time Limitation The PWM latch in Figure 2 is reset every cycle by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. The measured minimum off time is 00ns typically. If the required duty cycle is higher than the attainable maximum, then the output voltage will not be able toR6 VOits-set value in continuous-conduction R4 = reach 1 1.0 V mode. Inductor Selection D VO + V D= VIN + VD - VCESAT The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is
1 DV = DIL ESR + The inputOcapacitance must also be high enough to keep 8 FSW C O within specification. This is important input ripple voltage in reducing the conductive EMI from the regulator. The input capacitance can be estimated from
GPWM
R7 = AC =
( V V V ) (1 - D) + D R R4IL== 6 O O D - 1 FV 1.0SW L 1
(3)
where FSW is the switching frequency and L is the ( + +V inductance. VO VOVD ) D(1 - D) L 1== D VIN 20% -OVCESAT + VD I FSW An inductor ripple current between 20% to 50% of the maximum load current, IO, gives a good compromise IRMS _ CINV= IO cost and D) among efficiency, VD )D (11 - D) Re-arranging Equation (3) ( + ( - size. DIL = O and assuming 35% inductor ripple current, the inductor is FSW L 1 given by
( V + V ) (1 - D) 1 L 1 O = DIL ESR + DV = O D (4) 35V IO FSW FSW C O % 8 O -1 R4 = R6 If the input voltage varies over a wide range, then choose 1.0 V L based on the nominal input voltage. Always verify IRMS = I D (1 - D) converter _ CIN V O+ Vat the input voltage extremes. operation OI D D= C IN > + V O- V VIN DV F CESAT 4D The peak current IN SW SC4525A power transistor is at limit of least 3.6A. The maximum deliverable load current for the 1 DV = DIL ESR + SC4525AOis 3.6A minus one half of the inductor ripple ( V +VD ) (1 8 D)SW C O - F current.IL = O D FSW L 1
Input Decoupling Capacitor ( V + VD ) (1 - D) L 1 = O IO C IN > 20% I should be chosen to handle the RMS The input capacitorO FFSW 4 DVIN SW ripple current of a buck converter. This value is given by
IRMS _ CIN = IO D (1 - D)
(5)
I C R VO (6) C5 = R4IN=> 6 O - 1 41.VIN FSW D0 V AC = V 1 DV log the 1 Awhere20 IN is allowable input ripple voltage. FB C=- G R 2F C C8 = VO +S CO VOCA VD D= Multi-layerVceramic capacitors, which have very low ESR IN + VD - VCESAT 1 1 1 (a few mW) and can easily handle high RMS ripple current,.0 A C = - 20 log == R 15 -3 3 -6 are the ideal choice1for input 80 10 A single 4.7F.3 7 3 28 6. 10 2 filtering. 22 10 X5R ceramic( V + V ) (1 - D) capacitor is adequate for 500kHz or higher O D DIL frequency applications, and 0F is adequate C 5 = switching = 15.9 FSW L 1 for 200kHz to 500kHz switching frequency. For high 10 20 V R7 = =1 .3k 1 22 Avoltage applications, a small ceramic - 20 log-3 FB (F or 2.2F) can be C = C = 0.28 10 8 R ( VO G CAwith 2F) CESR VO - DC + VD )S (1a low O electrolytic capacitor to placedLin = parallel 1 1 20% I FSW Csatisfy both the3ESROand bulk = 0.45nF requirements. 5= capacitance 2 16 10 22.1 10 3 1 1 1.0 A C = - 20 log = 15 28 6.1 10 - 3 2 80 10 3 22 10 -6 3.3 Vo 1 Output Capacitor = C8 = I = 12pF Vc 2 RMS _ CIN 10O 22. (110D) 600 = I 3 D 1 - 3 The output .9 15 ripple voltage DVO of a buck converter can be 10 20 Rexpressed as -3 = 22.3k 7= GPWM Vo 0.28 10 (1 + sRESR C O ) GPWM = 1 2 Vc (1 DVO/= D)I(1 +ESR + Q + s 2 / n ) + s p L1 s / n (7) 8 3FSW0.C O nF C5 = = 45 3 2 16 10 22.1 10 where CO is the output capacitance. R7 = R 1 1 1 1 1 V,FB GPWM - 20 log, 3 Z = , C8 = = AC = G R p 3 C 12pF R as 2 the S G R ripple current 600 10 1 10 Since CA inductor22.2FC CR O VO DIL increasesESRC OD O CAO S I C IN decreases >(Equation (3)), the output ripple voltage is C 5 = AC 4 DV FSW therefore the IN 1 highest when V is at its maximum. 10 20 1 1.0 R7 = - 20 log (1 + sRESR C O )IN GPWM Vo AC = 15 -3 3 -6 = gm 3 .3 28 6.1 10 2 280 10 22 10 Vc 22F+to / p)(1 + s ceramic s 2 / n ) is found adequate C 8 = (1 s 47F X5R / n Q + capacitor A 1 Cfor=output filtering in most applications. Ripple current 5 2 FZ115.9 R in the10R20 7 capacitor is not a concern because the output 1 1 Rinductor = GPWM 1current= of a3kp converter directly=feeds C ,, , 22. buck , Z 7 0.28 10S-3 GCA R CO R ESRC OO Cresulting in very low rippleRcurrent. Avoid using Z5U 8= 2 FP1 R7 1 Cand Y5VC ceramic capacitors for output filtering because = 0.45nF A 5= 3 2 10 3 22.1 have 10 2016 of capacitors10 high temperature and high Rthese types 7= gm voltage coefficients. 1 C8 = = 12pF 2 600 10 3 22.1 10 3 1 CFreewheeling Diode 5= 2 FZ1 R7 G 1 + sR diodes Vo of Schottky (barrierESR C O ) as freewheeling rectifiers Use 1 PWM = Creduces sdiode(1reverse Q + s 2 / 2input current spikes, = (1 + / ) + s / recovery ) 8 Vc 2 F R p n n P1 7 easing high-side current sensing in the SC4525A. These GPWM R , GCA RS p 1 , RC O Z = 1 , R ESRC O
DV = DI ESR +
1

Fig 5
Applications Information (Cont.)
diodes should have an average forward current rating at least 3A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diode should be placed close to the SW pin of the SC4525A to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B320A, B330A (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and CMSH3-40MA (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4525A on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor The minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 4, which is about .98V at room temperature.
D1
SC4525A
SS270 REV 6-7
2.2 2.1 2.0 1.9 1.8 1.7 1.6 -50
Minimum Bootstrap Voltage vs Temperature
Voltage (V)
ISW =-3.9A
-25
0
25
50
75
100 125
Temperature (o C)
Figure 5. Typical Minimum Bootstrap Voltage required to Saturate Transistor (ISW= -3.9A)
D1 D3
BST VIN
C1 VOUT VIN
IN
SW
SC4525A
GND
D 2
(a) D3 D1
The BST-SW voltage is supplied by a bootstrap circuit C1 BST powered from either the input or the output of the VIN converter (Figure 5). To maximize SW efficiency, tie the VOUT IN bootstrap diode to the converter output if VO>2.5V. SC4525A D Since the bootstrap supply current is proportional to the 2 GND converter load current (Equation (0), page 4), using a lower voltage to power the bootstrap circuit reduces driving loss and improves efficiency. (a) For the bootstrap circuit, a fast switching PN diode (such as N448 or N94) and a small (0.F - 0.47F) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D. When bootstrapping from high input voltages (>20V), reduce the maximum BST voltage by connecting a Zener diode (D3) in series with D.
BST VIN
C1 VOUT
IN
SW
SC4525A
GND
D 2
(b)
Figure 6. Methods of Bootstrapping the SC4525A
Loop Compensation The goal of compensation is to shape the frequency response of the converter so as to achieve high DC accuracy and fast transient response while maintaining loop stability.
2
SC4525A
Applications Information (Cont.)
CONTROLLER AND SCHOTTKY DIODE Io
CA
Rs
REF
Including the voltage divider (R4 and R6), the control to feedback transfer function is found and plotted in Figure 8 as the converter gain.
SW L1 Vo
+ EA Vc
Vramp
FB
-
PWM MODULATOR
COMP C5 R7 C8 Co
R4
Resr
R6
Figure 7. Block diagram of control loops
1 VFB 1 1 A C diagram in 1 VFB The block= - 20 logFigure 7shows the control loops of a A C = - 20 log G R 2F C V CA S CO O G CA R S 2FC C O innerloop (current VO buck converter with the SC4525A. The loop) consists of a current sensing resistor (Rs=4.mW) 1 1 1 1 A C = - amplifier VFB and a current 20 log (CA) with gain (GCA=28). The outer -6 A C = - 20 log -3 3 2 80 10 3 22 10 28 6. of an 2 80 10 3 22 a -6 loop (voltage loop) consists1 10 - error amplifier (EA), 10 28 6.1 10 VO PWM modulator, and a LC filter. 1 Since R71= 10 1.0 = 15.9dB current 1 3 the = 10 loopis internally closed, the remaining 22 3k V -6 2 10 R7the0loop 10 - 3 = 22.3k is to design the voltage 0.28 compensation .28 3. - log 80task for22 10 FB1033 G CA R S 2FC C O (CV,OR, and C ). 1 compensator 5 7 1 8 C5 = = 0.45nF C5 = = 0.45nF 3 2 16 10 22.1 10 3 2 16 10 3 122.1 10 3 1.0 1 = F output log For a converter with switching frequency 15.,9dB SW 3 1 6.1 10 -= , output capacitance C 3 12pF 1 28inductance L 2 80 10 3 22 10 -6 = .3 loading R, the and pF C8 = C8 3 3O = 12 3 2 600 10 3 transfer function in Figure 7 is control (VC) 2 output (VO) 22.1 10 to 600 10 22.1 10 0.45nF given by: 15.9 = 22.3kV G (1 + sRESR C O ) GPWM (1 + sRESR C O ) o Vo = 10 -3pF = 12 = (1 + s / PWM + s / Q + s2 / 2 ) 2 2 Vc p )(1 n n Vc (1 + s / p )(1 + s / n Q + s / n ) 1 = 0.45nF 6 10 3 This1 10 3 function has a finite DC gain 22. transfer R 1 1 GPWM R , p 1 , GPWM 3= 12pF , p RC , 2 G R RC O / 2) 0010 3 22.1 10 GCA R S
n CA S O
20 15.9 15.9 20 20
Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ, and a high frequency pole at FP. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). The high frequency pole nulls the ESR zero and attenuates high frequency noise.
60 1.0 1.0 = 15.9dB 3.3 = 15.9dB 3 .3 30 GAIN (dB) Fz1 Fp1
CO MP EN SA TO RG AIN
0
Fp
Fc CO NV ER TER GA IN
LO OP GA IN
-30 Fz -60 1K Fsw/2
10K
100K FREQUENCY (Hz)
1M
10M
(8)
Figure 8. Bode plots for voltage loop design Therefore, the procedure of the voltage loop design for 1 the SC4525A can be summarized as: Z = 1 , Z = R C , ESR O R ESRC O () Plot the converter gain, i.e. control to feedback transfer function. (2) Select the open loop crossover frequency, FC, between 0% and 20% of the switching frequency. At FC, find the required compensator gain, AC. In typical applications with ceramic output capacitors, the ESR zero is neglected and the required compensator gain at FC can be estimated by
AC an ESR zero FZ at AC 20 10 20 101 R= 1 PWM (1 + sRESR7C= ) R7 = g G, Z O g m , m CO R / 2 / p )(1 + s / n Q + s 2ESRCnO) 1 1 C5 = C 5 = low-frequency pole FP at a dominant 2 F R Z1 7 2 FZ1 R7 1 1 , p , Z = , 1 C 8 = RC O1 = RS R ESRC O C 8 2 F R P1 7 2 FP1 R7 and double poles at half the switching frequency. V R4 = R6 O - 1 1.0 V
1 VFB 1 A C = - 20 log G R 2F C V CO O CA S
(9)
1 1 1.0 3 A C = - 20 log -3 3 -6 3. 2 80 10 22 10 28 6.1 10
C5 = C8 =
1 2 16 10 22.1 10 3
3
= 0.45nF
SC4525A
1 = 12pF 2 600 10 3 22.1 10 3
Applications Information (Cont.)
GPWM (1 + sRESR C O ) Vo (3) Place = compensator zero, FZ,2between 0% and the Thermal Considerations 2 Vc (1 + s / p )(1 + s / n Q + s / n ) 20% of the crossover frequency, FC. (4) Use the compensator pole, FP, to cancel the ESR zero, For the power transistor inside the SC4525A, the FZ. R 1 1 conduction loss PC, the switching loss PSW, and bootstrap GPWM , , Z = , (5) Then, the parameters of the pcompensation network C loss P = can be + PBST + PQ GCA RS RC O R ESR circuit PTOTAL BST,PC + PSWestimated as follows: O can be calculated by 10 20 R7 = gm 1 C5 = 2 FZ1 R7 1 C8 = 2 FP1 R7
where gm=0.28mA/V is the EA gain of the SC4525A. Example: Determine the voltage compensator for an 800kHz, 2V to 3.3V/3A converter with 47uF ceramic output capacitor.
AC
PC = D VCESAT IO PSW = 1 t S VIN I O FSW 2 IO 40
PQ = VIN 2mA
(0)
PBST = D VBST
where P BST is1 - D) V I voltage and tS is the equivalent V = ( the BST supply D DO switching time of the NPN transistor (see Table 4). Table 1 Typical I2 R DC PIND = (4..1 ~ 1.3)switching time O
Input Voltage 1A 12.5ns 22ns 25.3ns Load Current 2A 3A 15.3ns 18ns 25ns 28ns 28ns 31ns
12V Choose a loop gain crossover frequency of 80kHz, and 24V place voltage compensator zero 1 and pole FZ=6kHz 1 VFB at 28V A = - and F =600kHz. (20% ofC FC), 20 logP1 RVFB 2From Equation (9), the 1 G FC C O VO A C = - 20 log G R 2F CCA S required compensatorCgainVatFC is O O CA S PTOTAL = PC + PSW + PBST + PQ In addition, the quiescent current loss is 11 1.0 1 1.0 1 A C = -A C = - 20 log -3 20 log 19 = 3 dB = 19dB 33 -6 3 3 28 4.1 1028 2 .1 10 - 47 2 80 . 10 47 10 -6 3.3 80 10 10 4 () PQ = VIN 2mA PC = D VCESAT IO Then the compensator parameters are 10 19 R7 = = 31.8k The total power loss of the SC4525A is therefore 1 0.28 10 - 3 10 20 PSW = t S VIN I O FSW R7 = 1 = 31.8k 2 0.28 10 - 3 = 0.31nF C5 = PTOTAL = PC + PSW + PBST + PQ (2) 2 16 10 3 31.4 10 3 IO 1 C5 = 1 = 0.31nF VBST PBST = D 3 = 8.5pF 3 C8 = 40 The temperature rise of the SC4525A PQtheVproduct of the is = IN 2mA 2 600 2 3 16 .4 10 3 31 .4 10 10 31 10 PC = D VCESAT IO total power dissipation (Equation (2)) and qJA (36oC/W), 1 C 8 = (1 + sR C )3 = 8.5pF which is the thermal impedance from junction to ambient 1 GPWM Vo ESR O 2 600 10 2 31.4 10 3 PD = (1 - D) VD IO = 2 for thePSW = 2 EDPpackage. SW SOIC-8 t S VIN I O F Vc (1 + s / p )(1 + s / n Q + s / n ) Select R7=3.4k, C5=0.33nF, and C8=0pF for the design. 2 I It 1 GPWM (1 + ,sRESR C O )Z PIND 1= (1.1 ~ 1.3) IO R DC is not recommended to operate the SC4525A above Vo R , PBST = D VBST O GPWM p = , G =RS R R ESRC 40 Compensator parametersCfor various 2typical applications 25oC junction temperature. In the applications with high 2 VcCA (1 + s / p )(1 + O / n Q + s / n )O s are listed in Table 5. A MathCAD program is also available input voltage and high output current, the switching 10 upon request for detailed calculation of the compensator frequency may D) VD toObe reduced to meet the thermal R7 = PD = (1 - need I gm parameters. R 1 1 requirement. GPWM , p , Z = , 1 GCA RS RC O R ESRC O C5 = 2 FZ 1 R7 PIND = (1.1 ~ 1.3) I2 R DC O
19 20 AC 20
C8 =
AC 1 20 2RFP1= 7 R 10
7
gm
C5 =
1
4
SC4525A
Applications Information (Cont.)
PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4525A, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device.
V IN
VOUT
ZL
Figure 9. Heavy lines indicate the critical pulse current loop. The inductance of this loop should be minimized.
Vin
Curre nts in Power Section
5
SC4525A
Recommended Component Parameters in Typical Applications
Table 5 lists the recommended inductance (L) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/0. Table 5. Recommended inductance (L1) and compensator (R7, C5, C8)
Vin(V) Typical Applications Vo(V) Io(A) Fsw(kHz) C2(uF) Recommended Parameters L1(uH) R7(k) C5(nF) C8(pF)
1.5 2.5 3.3
12
5 7.5 10 1.5 2.5 3.3
3
24
5 7.5 10
3
500 500 1000 500 1000 500 1000 500 1000 500 1000 300 500 1000 500 1000 500 1000 500 1000 500 1000
47
47
3.3 4.7 2.2 6.8 3.3 6.8 3.3 6.8 3.3 3.3 2.2 6.8 6.8 2.2 6.8 3.3 8.2 4.7 10 4.7 15 6.8
10 16.2 29.4 23.2 39.2 29.4 69.8 43.2 90.9 69.8 133 6.81 12.4 29.4 23.2 43.2 29.4 59 49.9 100 59 133
2.2 2.2 0.47 2.2 0.47 2.2 0.47 2.2 0.47 2.2 0.47 2.2 2.2 0.47 2.2 0.47 2.2 0.47 2.2 0.47 2.2 0.47
10
10
6
SC4525A
Typical Application Schematics
D3 D1
V
IN
24V C4 4.7mF
18V Zener 1N4148 IN BST SW SS/EN
C1 0.33mF L1 6.8mH R4 33.2k
OUT 1.5V/3A
SC4525A
FB
COMP C7 10nF R7 6.81k
ROSC
GND D2 B330A R6 66.5k C2 47mF
C8 22pF
R5 90.9k
C5 2.2nF
L1: Coiltronics DR74-6R8
C2: Murata GRM31CR60J476M C4: Murata GRM32ER71H475K
Figure 10. 300kHz 24V to 1.5V/3A Step-down Converter
EVB#d: 300kHz 24V to 1.5V/3A Step-Down Converter
V IN 10V - 26V C4 4.7mF D1 1N4148 C1 0.1mF L1 3.3mH R4 33.2k
IN
BST SW
OUT 3.3V/3A
SS/EN
SC4525A
FB
COMP C7 10nF R7 43.2k
ROSC
GND D2 B330A R6 14.3k C2 47mF
C8 10pF
R5 18.2k
C5 0.47nF
L1: Coiltronics DR74-3R3
C2: Murata GRM31CR60J476M C4: Murata GRM32ER71H475K
Figure 11. 1MHz 10V-26V to 3.3V/3A Step-down Converter
1MHz 10V-26V to 3.3V/3A Step-Down Converter
7
SC4525A
SS
Typical Performance Characteristics
SS270 REV 6-7
(For A 12V to 5V/3A Step-down Converter with 1MHz Switching Frequency)
Load Characteristic
6 5
Output Voltage (V)
4 3
12V Input (5V/DIV)
5V Output (2V/DIV)
2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
SS Voltage (1V/DIV)
Load Current (A)
10ms/DIV
Figure 12(a). Load Characteristic
OCP
Figure 12(b). VIN Start up Transient (IO=3A)
5V Output Short (5V/DIV)
5V Output Response (500mV/DIV, AC Coupling)
Inductor Current (1A/DIV)
Retry Inductor Current (2A/DIV)
SS Voltage (2V/DIV)
40us/DIV
20ms/DIV
Figure 12(c). Load Transient Response (IO= 0.3A to 3A)
Figure 12(d). Output Short Circuit (Hiccup)
8
SC4525A
SO-8 EDP2 Outline
Outline Drawing - SOIC-8 EDP
A N 2X E/2 E1 E 1 ccc C 2X N/2 TIPS 2 e/2 B D aaa C SEATING PLANE A2 A A1 C A-B D e D
DIM
A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .000 .005 .049 .065 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.35 1.75 0.00 0.13 1.25 1.65 0.31 0.51 0.17 0.25 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0 8 0.10 0.25 0.20
C
bxN bbb F
h
EXPOSED PAD H
H GAGE PLANE 0.25
h
c
L (L1)
01
SEE DETAIL SIDE VIEW
NOTES: 1.
A
DETAIL
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION BA.
SO-8 EDP2 Landing Pattern
E D
Land Pattern - SOIC-8 EDP
SOLDER MASK
DIM
(C) F G Z C D E F G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .134 .201 .101 .118 .050 .024 .087 .291 (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40
Y THERMAL VIA O 0.36mm
NOTES:
P X
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation Power Mangement Products Division 200 Flynn Road, Camarillo, CA 9302 Phone: (805) 498-2 Fax: (805) 498-3804
9

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